uint16_t max_num_addressable_ids_logical
Maximum number of addressable IDs for logical processors sharing this cache.
Definition: cpuid_0x04h.h:29
uint8_t write_back
Write-Back Invalidate/Invalidate.
Definition: cpuid_0x04h.h:63
uint32_t s
Number of Sets.
Definition: cpuid_0x04h.h:54
cpuid_0x04h_eax_fields eax
EAX fields.
Definition: cpuid_0x04h.h:80
uint8_t cache_level
Cache Level (starts at 1).
Definition: cpuid_0x04h.h:20
uint16_t p
Physical Line partitions.
Definition: cpuid_0x04h.h:43
uint16_t l
System Coherency Line Size.
Definition: cpuid_0x04h.h:40
uint8_t cache_inclusiveness
Cache Inclusiveness.
Definition: cpuid_0x04h.h:67
Intel thread/core and cache topology.
Definition: cpuid_0x04h.h:77
uint8_t self_init_cache_level
Self Initializing cache level (does not need SW initialization).
Definition: cpuid_0x04h.h:22
cpuid_0x04h_ecx_fields ecx
ECX fields.
Definition: cpuid_0x04h.h:84
cpuid_0x04h_edx_fields edx
EDX fields.
Definition: cpuid_0x04h.h:86
uint8_t copmlex_cache_indexing
Complex Cache Indexing.
Definition: cpuid_0x04h.h:71
Write-Back Invalidate/Invalidate, Cache Inclusiveness, Complex Cache Indexing.
Definition: cpuid_0x04h.h:58
uint8_t fully_associative_cache
Fully Associative cache.
Definition: cpuid_0x04h.h:24
cpuid_0x04h_fields fields
Separate fields.
Definition: cpuid_0x04h.h:95
Intel thread/core and cache topology.
Definition: cpuid_0x04h.h:90
uint8_t cache_type_field
Cache Type Field.
Definition: cpuid_0x04h.h:18
cpuid_0x04h_ebx_fields ebx
EBX fields.
Definition: cpuid_0x04h.h:82
uint16_t w
Ways of associativity.
Definition: cpuid_0x04h.h:46
System Coherency Line Size, Physical Line partitions and Ways of associativity.
Definition: cpuid_0x04h.h:36
size_t uint32_t
Unsigned integral type.
Definition: string.h:8
Number of Sets.
Definition: cpuid_0x04h.h:50
Intel thread/core and cache topology.
Definition: cpuid_0x04h.h:7
uint8_t max_num_addressable_ids_physical
Maximum number of addressable IDs for processor cores in the physical package.
Definition: cpuid_0x04h.h:32