MicrOS
cpuid_0x01h.h
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1 #ifndef CPUID_0x01H_H
2 #define CPUID_0x01H_H
3 
4 #include <stdint.h>
5 
7 typedef struct cpuid_0x01h_eax_fields
8 {
10  uint8_t stepping_id : 4;
12  uint8_t model : 4;
14  uint8_t family_id : 4;
16 
23  uint8_t procesor_type : 2;
24  // Reserved
25  uint8_t : 2;
27  uint8_t extended_model_id : 4;
29  uint8_t extended_family_id : 8;
30  // Reserved
31  uint8_t : 4;
32 } __attribute__((packed)) cpuid_0x01h_eax_fields;
33 
35 typedef struct cpuid_0x01h_ebx_fields
36 {
38  uint8_t brand_index;
40 
44 
52 
55  uint8_t local_apic_id;
56 } __attribute__((packed)) cpuid_0x01h_ebx_fields;
57 
59 typedef struct cpuid_0x01h_ecx_fields
60 {
62  uint8_t sse3 : 1;
64  uint8_t pclmulqdq : 1;
66  uint8_t dtes64 : 1;
68  uint8_t monitor : 1;
70  uint8_t ds_cpl : 1;
72  uint8_t vmx : 1;
74  uint8_t smx : 1;
76  uint8_t est : 1;
77 
79  uint8_t tm2 : 1;
81  uint8_t ssse3 : 1;
83  uint8_t cnxt_id : 1;
85  uint8_t sdbg : 1;
87  uint8_t fma : 1;
89  uint8_t cx16 : 1;
91  uint8_t xtpr : 1;
93  uint8_t pdcm : 1;
94 
95  // Reserved
96  uint8_t : 1;
98  uint8_t pcid : 1;
100  uint8_t dca : 1;
102  uint8_t sse4_1 : 1;
104  uint8_t sse4_2 : 1;
106  uint8_t x2apic : 1;
108  uint8_t movbe : 1;
110  uint8_t popcnt : 1;
111 
113  uint8_t tsc_deadline : 1;
115  uint8_t aes : 1;
117  uint8_t xsave : 1;
119  uint8_t osxsave : 1;
121  uint8_t avx : 1;
123  uint8_t f16c : 1;
125  uint8_t rdrnd : 1;
127  uint8_t hypervisor : 1;
128 } __attribute__((packed)) cpuid_0x01h_ecx_fields;
129 
132 {
134  uint8_t fpu : 1;
136  uint8_t vme : 1;
138  uint8_t de : 1;
140  uint8_t pse : 1;
142  uint8_t tsc : 1;
144  uint8_t msr : 1;
146  uint8_t pae : 1;
148  uint8_t mce : 1;
149 
151  uint8_t cx8 : 1;
153  uint8_t apic : 1;
154  // Reserved
155  uint8_t : 1;
157  uint8_t sep : 1;
159  uint8_t mtrr : 1;
161  uint8_t pge : 1;
163  uint8_t mca : 1;
165  uint8_t cmov : 1;
166 
168  uint8_t pat : 1;
170  uint8_t pse_32: 1;
172  uint8_t psn : 1;
174  uint8_t clfsh : 1;
175  // Reserved
176  uint8_t : 1;
178  uint8_t ds : 1;
180  uint8_t acpi : 1;
182  uint8_t mmx : 1;
183 
185  uint8_t fxsr : 1;
187  uint8_t sse : 1;
189  uint8_t sse2 : 1;
191  uint8_t ss : 1;
193  uint8_t htt : 1;
195  uint8_t tm : 1;
197  uint8_t ia64 : 1;
199  uint8_t pbe : 1;
200 } __attribute__((packed)) cpuid_0x01h_edx_fields;
201 
203 typedef struct cpuid_0x01h_fields
204 {
206  /*!//! CPU's stepping, model, and family information*/
209  /*!//! CPU additional information.*/
212  /*!//! CPU features from ECX register.*/
215  /*!//! CPU features from EDX register.*/
218 
220 typedef union cpuid_0x01h
221 {
223  uint32_t value[4];
226 } cpuid_0x01h;
227 
228 #endif
CPU&#39;s stepping, model, and family information.
Definition: cpuid_0x01h.h:7
Processor Info and Feature Bits.
Definition: cpuid_0x01h.h:203
uint8_t popcnt
POPCNT instruction.
Definition: cpuid_0x01h.h:110
uint8_t fxsr
FXSAVE, FXRESTOR instructions, CR4 bit 9.
Definition: cpuid_0x01h.h:185
uint8_t clflush_line_size
CLFLUSH line size.
Definition: cpuid_0x01h.h:42
uint8_t max_number_of_addressable_ids
Maximum number of addressable IDs for logical processors in this physical package.
Definition: cpuid_0x01h.h:50
uint8_t ds
Debug store: save trace of executed jumps.
Definition: cpuid_0x01h.h:178
uint8_t htt
Hyper-threading.
Definition: cpuid_0x01h.h:193
uint8_t tsc_deadline
APIC implements one-shot operation using a TSC deadline value.
Definition: cpuid_0x01h.h:113
Processor Info and Feature Bits.
Definition: cpuid_0x01h.h:220
uint8_t pat
Page Attribute Table.
Definition: cpuid_0x01h.h:168
uint8_t fma
Fused multiply-add (FMA3)
Definition: cpuid_0x01h.h:87
uint8_t de
Debugging extensions (CR4 bit 3)
Definition: cpuid_0x01h.h:138
uint8_t xtpr
Can disable sending task priority messages.
Definition: cpuid_0x01h.h:91
uint8_t ss
CPU cache implements self-snoop.
Definition: cpuid_0x01h.h:191
uint8_t sse3
Prescott New Instructions-SSE3 (PNI)
Definition: cpuid_0x01h.h:62
uint8_t ia64
IA64 processor emulating x86.
Definition: cpuid_0x01h.h:197
uint8_t tm
Thermal monitor automatically limits temperature.
Definition: cpuid_0x01h.h:195
uint8_t vme
Virtual 8086 mode extensions (such as VIF, VIP, PIV)
Definition: cpuid_0x01h.h:136
uint8_t cmov
Conditional move and FCMOV instructions.
Definition: cpuid_0x01h.h:165
uint8_t psn
Processor Serial Number.
Definition: cpuid_0x01h.h:172
uint8_t mca
Machine check architecture.
Definition: cpuid_0x01h.h:163
uint8_t avx
Advanced Vector Extensions.
Definition: cpuid_0x01h.h:121
uint8_t smx
Safer Mode Extensions (LaGrande)
Definition: cpuid_0x01h.h:74
uint8_t vmx
Virtual Machine eXtensions.
Definition: cpuid_0x01h.h:72
uint8_t pae
Physical Address Extension.
Definition: cpuid_0x01h.h:146
uint8_t model
Model.
Definition: cpuid_0x01h.h:12
uint8_t cx8
CMPXCHG8 (compare-and-swap) instruction.
Definition: cpuid_0x01h.h:151
uint8_t apic
Onboard Advanced Programmable Interrupt Controller.
Definition: cpuid_0x01h.h:153
uint8_t sdbg
Silicon Debug interface.
Definition: cpuid_0x01h.h:85
uint8_t aes
AES instruction set.
Definition: cpuid_0x01h.h:115
cpuid_0x01h_fields fields
Separate fields.
Definition: cpuid_0x01h.h:225
uint8_t osxsave
XSAVE enabled by OS.
Definition: cpuid_0x01h.h:119
cpuid_0x01h_eax_fields eax
EAX fields.
Definition: cpuid_0x01h.h:207
uint8_t pbe
Pending Break Enable (PBE# pin) wakeup capability.
Definition: cpuid_0x01h.h:199
uint8_t pse
Page Size Extension.
Definition: cpuid_0x01h.h:140
uint8_t mmx
MMX instructions.
Definition: cpuid_0x01h.h:182
uint8_t est
Enhanced SpeedStep.
Definition: cpuid_0x01h.h:76
uint8_t stepping_id
Stepping ID.
Definition: cpuid_0x01h.h:10
uint8_t movbe
MOVBE instruction (big-endian)
Definition: cpuid_0x01h.h:108
uint8_t monitor
MONITOR and MWAIT instructions (SSE3)
Definition: cpuid_0x01h.h:68
uint8_t tm2
Thermal Monitor 2.
Definition: cpuid_0x01h.h:79
uint8_t extended_family_id
Extended family ID.
Definition: cpuid_0x01h.h:29
uint8_t mce
Machine Check Exception.
Definition: cpuid_0x01h.h:148
uint8_t f16c
F16C (half-precision) FP feature.
Definition: cpuid_0x01h.h:123
uint8_t dtes64
64-bit debug store (edx bit 21)
Definition: cpuid_0x01h.h:66
uint8_t local_apic_id
Local APIC ID.
Definition: cpuid_0x01h.h:55
uint8_t family_id
Family ID.
Definition: cpuid_0x01h.h:14
uint8_t ds_cpl
CPL qualified debug store.
Definition: cpuid_0x01h.h:70
uint8_t fpu
Onboard x87 FPU.
Definition: cpuid_0x01h.h:134
uint8_t rdrnd
RDRAND (on-chip random number generator) feature.
Definition: cpuid_0x01h.h:125
uint8_t sse4_1
SSE4.1 instructions.
Definition: cpuid_0x01h.h:102
cpuid_0x01h_ecx_fields ecx
ECX fields.
Definition: cpuid_0x01h.h:213
uint8_t sse2
SSE2 instructions.
Definition: cpuid_0x01h.h:189
uint8_t acpi
Onboard thermal control MSRs for ACPI.
Definition: cpuid_0x01h.h:180
CPU features from EDX register.
Definition: cpuid_0x01h.h:131
uint8_t hypervisor
Hypervisor present (always zero on physical CPUs)
Definition: cpuid_0x01h.h:127
uint8_t pse_32
36-bit page size extension
Definition: cpuid_0x01h.h:170
uint8_t xsave
XSAVE, XRESTOR, XSETBV, XGETBV.
Definition: cpuid_0x01h.h:117
uint8_t brand_index
Brand index.
Definition: cpuid_0x01h.h:38
uint8_t pdcm
Perfmon & debug capability.
Definition: cpuid_0x01h.h:93
uint8_t mtrr
Memory Type Range Registers.
Definition: cpuid_0x01h.h:159
uint8_t dca
Direct cache access for DMA writes.
Definition: cpuid_0x01h.h:100
uint8_t tsc
Time Stamp Counter.
Definition: cpuid_0x01h.h:142
uint8_t cnxt_id
L1 Context ID.
Definition: cpuid_0x01h.h:83
cpuid_0x01h_ebx_fields ebx
EBX fields.
Definition: cpuid_0x01h.h:210
uint8_t pclmulqdq
PCLMULQDQ.
Definition: cpuid_0x01h.h:64
uint8_t pcid
Process context identifiers (CR4 bit 17)
Definition: cpuid_0x01h.h:98
uint8_t cx16
CMPXCHG16B instruction.
Definition: cpuid_0x01h.h:89
size_t uint32_t
Unsigned integral type.
Definition: string.h:8
uint8_t sep
SYSENTER and SYSEXIT instructions.
Definition: cpuid_0x01h.h:157
uint8_t ssse3
Supplemental SSE3 instructions.
Definition: cpuid_0x01h.h:81
CPU additional information.
Definition: cpuid_0x01h.h:35
uint8_t extended_model_id
Extended model ID.
Definition: cpuid_0x01h.h:27
uint8_t sse
SSE instructions (a.k.a. Katmai New Instructions)
Definition: cpuid_0x01h.h:187
uint8_t msr
Model-specific registers.
Definition: cpuid_0x01h.h:144
uint8_t clfsh
CLFLUSH instruction (SSE2)
Definition: cpuid_0x01h.h:174
CPU features from ECX register.
Definition: cpuid_0x01h.h:59
uint8_t procesor_type
Procesor type.
Definition: cpuid_0x01h.h:23
cpuid_0x01h_edx_fields edx
EDX fields.
Definition: cpuid_0x01h.h:216
uint8_t x2apic
x2APIC
Definition: cpuid_0x01h.h:106
uint8_t sse4_2
SSE4.2 instructions.
Definition: cpuid_0x01h.h:104
uint8_t pge
Page Global Enable bit in CR4.
Definition: cpuid_0x01h.h:161