CPU features from ECX register. More...

#include <cpuid_0x01h.h>

Public Attributes
uint8_t	sse3: 1
	Prescott New Instructions-SSE3 (PNI) More...

uint8_t	pclmulqdq: 1
	PCLMULQDQ. More...

uint8_t	dtes64: 1
	64-bit debug store (edx bit 21) More...

uint8_t	monitor: 1
	MONITOR and MWAIT instructions (SSE3) More...

uint8_t	ds_cpl: 1
	CPL qualified debug store. More...

uint8_t	vmx: 1
	Virtual Machine eXtensions. More...

uint8_t	smx: 1
	Safer Mode Extensions (LaGrande) More...

uint8_t	est: 1
	Enhanced SpeedStep. More...

uint8_t	tm2: 1
	Thermal Monitor 2. More...

uint8_t	ssse3: 1
	Supplemental SSE3 instructions. More...

uint8_t	cnxt_id: 1
	L1 Context ID. More...

uint8_t	sdbg: 1
	Silicon Debug interface. More...

uint8_t	fma: 1
	Fused multiply-add (FMA3) More...

uint8_t	cx16: 1
	CMPXCHG16B instruction. More...

uint8_t	xtpr: 1
	Can disable sending task priority messages. More...

uint8_t	pdcm: 1
	Perfmon & debug capability. More...

uint8_t	__pad0__: 1

uint8_t	pcid: 1
	Process context identifiers (CR4 bit 17) More...

uint8_t	dca: 1
	Direct cache access for DMA writes. More...

uint8_t	sse4_1: 1
	SSE4.1 instructions. More...

uint8_t	sse4_2: 1
	SSE4.2 instructions. More...

uint8_t	x2apic: 1
	x2APIC More...

uint8_t	movbe: 1
	MOVBE instruction (big-endian) More...

uint8_t	popcnt: 1
	POPCNT instruction. More...

uint8_t	tsc_deadline: 1
	APIC implements one-shot operation using a TSC deadline value. More...

uint8_t	aes: 1
	AES instruction set. More...

uint8_t	xsave: 1
	XSAVE, XRESTOR, XSETBV, XGETBV. More...

uint8_t	osxsave: 1
	XSAVE enabled by OS. More...

uint8_t	avx: 1
	Advanced Vector Extensions. More...

uint8_t	f16c: 1
	F16C (half-precision) FP feature. More...

uint8_t	rdrnd: 1
	RDRAND (on-chip random number generator) feature. More...

uint8_t	hypervisor: 1
	Hypervisor present (always zero on physical CPUs) More...

Detailed Description

CPU features from ECX register.

Member Data Documentation

◆ pad0

uint8_t cpuid_0x01h_ecx_fields::__pad0__

◆ aes

uint8_t cpuid_0x01h_ecx_fields::aes

AES instruction set.

◆ avx

uint8_t cpuid_0x01h_ecx_fields::avx

Advanced Vector Extensions.

◆ cnxt_id

uint8_t cpuid_0x01h_ecx_fields::cnxt_id

L1 Context ID.

◆ cx16

uint8_t cpuid_0x01h_ecx_fields::cx16

CMPXCHG16B instruction.

◆ dca

uint8_t cpuid_0x01h_ecx_fields::dca

Direct cache access for DMA writes.

◆ ds_cpl

uint8_t cpuid_0x01h_ecx_fields::ds_cpl

CPL qualified debug store.

◆ dtes64

uint8_t cpuid_0x01h_ecx_fields::dtes64

64-bit debug store (edx bit 21)

◆ est

uint8_t cpuid_0x01h_ecx_fields::est

Enhanced SpeedStep.

◆ f16c

uint8_t cpuid_0x01h_ecx_fields::f16c

F16C (half-precision) FP feature.

◆ fma

uint8_t cpuid_0x01h_ecx_fields::fma

Fused multiply-add (FMA3)

◆ hypervisor

uint8_t cpuid_0x01h_ecx_fields::hypervisor

Hypervisor present (always zero on physical CPUs)

◆ monitor

uint8_t cpuid_0x01h_ecx_fields::monitor

MONITOR and MWAIT instructions (SSE3)

◆ movbe

uint8_t cpuid_0x01h_ecx_fields::movbe

MOVBE instruction (big-endian)

◆ osxsave

uint8_t cpuid_0x01h_ecx_fields::osxsave

XSAVE enabled by OS.

◆ pcid

uint8_t cpuid_0x01h_ecx_fields::pcid

Process context identifiers (CR4 bit 17)

◆ pclmulqdq

uint8_t cpuid_0x01h_ecx_fields::pclmulqdq

PCLMULQDQ.

◆ pdcm

uint8_t cpuid_0x01h_ecx_fields::pdcm

Perfmon & debug capability.

◆ popcnt

uint8_t cpuid_0x01h_ecx_fields::popcnt

POPCNT instruction.

◆ rdrnd

uint8_t cpuid_0x01h_ecx_fields::rdrnd

RDRAND (on-chip random number generator) feature.

◆ sdbg

uint8_t cpuid_0x01h_ecx_fields::sdbg

Silicon Debug interface.

◆ smx

uint8_t cpuid_0x01h_ecx_fields::smx

Safer Mode Extensions (LaGrande)

◆ sse3

uint8_t cpuid_0x01h_ecx_fields::sse3

Prescott New Instructions-SSE3 (PNI)

◆ sse4_1

uint8_t cpuid_0x01h_ecx_fields::sse4_1

SSE4.1 instructions.

◆ sse4_2

uint8_t cpuid_0x01h_ecx_fields::sse4_2

SSE4.2 instructions.

◆ ssse3

uint8_t cpuid_0x01h_ecx_fields::ssse3

Supplemental SSE3 instructions.

◆ tm2

uint8_t cpuid_0x01h_ecx_fields::tm2

Thermal Monitor 2.

◆ tsc_deadline

uint8_t cpuid_0x01h_ecx_fields::tsc_deadline

APIC implements one-shot operation using a TSC deadline value.

◆ vmx

uint8_t cpuid_0x01h_ecx_fields::vmx

Virtual Machine eXtensions.

◆ x2apic

uint8_t cpuid_0x01h_ecx_fields::x2apic

x2APIC

◆ xsave

uint8_t cpuid_0x01h_ecx_fields::xsave

XSAVE, XRESTOR, XSETBV, XGETBV.

◆ xtpr

uint8_t cpuid_0x01h_ecx_fields::xtpr

Can disable sending task priority messages.

The documentation for this struct was generated from the following file:

os/kernel/src/cpu/cpuid/headers/cpuid_0x01h.h

Public Attributes